View MT9M011_1074153.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MT9M011 - 1/3-inch megapixel image sensor features preliminary ? pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_1.fm - rev. d 1/05 en 1 ?2004 micron technology, inc. all rights reserved. ?products and specifications discus sed herein are for evaluation a nd reference purposes only and ar e subject to change by micro n without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 1/3-inch megapixel cmos active-pixel digital image sensor MT9M011 for the latest data sheet revision, please refer to micron?s web site: www.micron.com/imaging features ? digitalclarity ? cmos imaging technology high frame rate superior low-light performance low dark current simple two-wire serial interface auto black level calibration operating modes: snapshot and flash control, high frame rate preview, electronic panning programmable controls: gain, frame size/rate, exposure, left-right and top- bottom image reversal, window size, and panning applications cellular phones pdas toys other battery-powered products general description the micron ? imaging MT9M011 is an sxga-format, 1/3-inch cmos active-pixel digital image sensor with an active imaging pixel array of 1,280h x 1,024v. it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. it is programmable through a simple two-wire serial interface and has low power consump- tion. the megapixel cmos image sensor features digital- clarity?micron?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ra tio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. the sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. the default mode outputs an sxga image at 13.9 frames per second (fps). an on-chip analog-to-digital converter (adc) provides 10 bits per pixel. frame_valid and line_valid sig- nals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. a flash out- put signal is also available to synchronize external light sources with sensor exposure time. table 1: key performance parameters parameter typical value optical format 1/3-inch (5:4) active imager size 4.6mm(h) x 3.7mm(v), 5.9mm (diagonal) active pixels 1,280h x 1,024v pixel size 3.6m x 3.6m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 25 mps/25 mhz frame rate sxga (1280 x 1024) programmable up to 15 fps vga (640 x 480) programmable up to 60 fps cif (352 x 288) programmable up to 150 fps adc resolution 10-bit, on-chip responsivity 1.0 v/lux-sec (550nm) dynamic range >71db snr max 44db supply voltage i/o digital 1.7v ? 3.6v core digital 2.5v ? 3.1v (2.8v nominal) analog 2.5v ? 3.1v (2.8v nominal) power consumption 129mw (full resolution mode) 70mw (preview mode) operating temperature -30c to +70c
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011toc.fm - rev. d 1/05 en 2 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor table of contents preliminary ? table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 two-wire serial interface sample write an d read sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 eight-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 eight-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 border of pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 column mirror image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 row mirror image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 column and row skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 digital zoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 readout speeds and power savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 minimum horizontal blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 valid data signals options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 line_valid signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 frame_valid signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 integration time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 maximum shutter delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 flash description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 recommended gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 propagation delay for frame_valid and line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011lof.fm - rev. d 1/05 en 3 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor list of figures preliminary ? list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 5: spatial illustration of image re adout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 6: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 7: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 8: timing diagram showing a write to reg0x09 with the va lue 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: timing diagram showing a read from reg0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: timing diagram showing a write to reg0x09 with the value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 figure 11: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .15 figure 12: readout of 6 pixels in normal and column mirror outp ut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13: readout of 6 rows in normal and row mirror output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 14: readout of 8 pixels in normal and column skip 2x ou tput mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 15: readout of 16 pixels in normal and column skip 4x output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8 figure 16: readout of 8 pixels in normal and zoom 2x output mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 17: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 18: frame_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 19: xenon flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 20: led flash enabled (int egration time = number of rows in a frame). . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: led flash enabled with restart (integration time = number of rows in a frame) . . . . . . . . . . . . . . . .33 figure 22: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 7 figure 23: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 24: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 25: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 26: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 30: acknowledge signal timing after an 8-bit read from the sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 31: spectral response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011lot.fm - rev. d 1/05 en 4 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor list of tables preliminary ? list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 3: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: register list and default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6: reserved register list and default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7: register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: recommended gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 9: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 10: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 5 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor preliminary ? figure 1: block diagram figure 2: typical configuration (connection) notes: 1. resistor value 1.5k ? is recommended, but may be great er for slower two-wire speed. 2. v dd and v aa supplies must be at same potential to avoid excess current draw. care must be taken to avoid noise inject ion in the analog supply is ca ses where a single supply is used. serial i/o data out sync signals control register analog processing active pixel sensor (aps) array sxga 1,316h x 1,048v timing and control adc 1k ? 1.5k ? d g nd d g nd qa g nd 2.8v analo g 2.8v i/o 2.8v di g it al ma s ter c lo c k (25 mhz) a g nd d g nd d g nd q d g nd q + 10 f + 1f 0.1f + 1f + 1f v dd sc lk vaapix v dd q s data v aa d g nd pix c lk re s et# s ta n d b y c lkin a g nd oe# d out3 d g nd q fla s h frame_valid line_va lid d out1 d out 6 d out2 d out9 d out5 d out0 d out8 d out7 d out4 1.5k ? 0.1f 0.1f two-wire s erial bus
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 6 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor preliminary ? table 2: signal description name type description reset# input asynchronous reset of sensor when low. all registers reset to factory defaults. standby input enables low power standby mode when = 1. oe# input enables output drivers when = 0. sclk input serial clock. clkin input master clock into sensor (25 mhz maximum). s data i/o serial data. line_valid output line valid: active high during line of selectable valid pixel data (see reg0x20 for options). frame_valid output frame valid: active high during frame of valid pixel data. flash output synchronization pulse for external light source. pixclk output pixel clock output. pixel data ou tputs are valid during rising edge of this clock. d out 0output pixel data output bit 0 (lsb). d out 1output pixel data output bit 1. d out 2output pixel data output bit 2. d out 3output pixel data output bit 3. d out 4output pixel data output bit 4. d out 5output pixel data output bit 5. d out 6output pixel data output bit 6. d out 7output pixel data output bit 7. d out 8output pixel data output bit 8. d out 9output pixel data output bit 9 (msb). v dd qpower digital i/o power. v aa power analog power. vaapix power pixel array power. v dd power digital core power. a gnd ground analog ground. d gnd ground digital core ground. d gnd qground digital i/o ground. nc ? no connect.
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 7 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor pixel data format preliminary ? pixel data format pixel array structure the MT9M011 pixel array is configured as 1,316 columns by 1,048 rows (shown in figure 3). the first 26 columns and the first ei ght rows of pixels are optically black, and can be used to monitor the black level. the last column and the last seven rows of pixels are also optically black. the black row data is used internally for the automatic black level adjustment. however, the first eight blac k rows can also be read out by setting the sensor to raw data output mode (reg0x22). there are 1,289 columns by 1,033 rows of optically active pixels, which provides a fo ur-pixel boundary around the sxga (1,280 x 1,024) image to avoid boundary effects during color interpolation and correction. the additional active column and additional acti ve row are used to allow horizontally and vertically mirrored readout to al so start on the same color pixel. figure 3: pixel array description the MT9M011 uses a bayer color pattern, shown in figure 4. the even-numbered rows contain green and red color pixels, and od d-numbered rows contain blue and green color pixels. even-numbered columns contai n green and blue color pixels; odd-num- bered columns contain red and green color pixels. figure 4: pixel color pattern detail (top right corner) (1315, 1047) 2 6 b la c k c olumns 7 b la c k rows 8 b la c k rows (0, 0) 1 b la c k c olumn s x g a (1,280 x 1,024) + 4 pixel b oun d ary for c olor c orre c tion + a dd itional a c tive c olumn + a dd itional a c tive row = 1,289 x 1,033 a c tive pixels pixel (2 6 , 8) b la c k pixels c olumn rea d out d ire c tion . . . ... row rea d out d ire c tion g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 8 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor pixel data format preliminary ? output data format the MT9M011 image data is read out in a progressive scan. valid image data is sur- rounded by horizontal blanking and vertical blanking, as shown in figure 5. the amount of horizontal blanking is programmable th rough reg0x05 and reg0x07; while vertical blanking is programmable th rough reg0x06 and reg0x08, re spectively. line_valid is high during the shaded region of the figure. frame_valid timing is described in ?out- put data timing? on page 9. figure 5: spatial illust ration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 9 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor pixel data format preliminary ? output data timing the data output of the MT9M011 is synchronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. the pix- clk signal is nominally the inverted of the master clock, allowing pixclk to be used as a clock to latch the data. it is continuously enabled, even during the blanking period. the MT9M011 can be programmed to delay the pixclk edge relative to the d out transitions from 0 to 3.5 master clocks, in steps of one- half of a master clock. this is achieved by programming the corresponding bits in reg0x0a. the parameters p, a, and q in figure 7 are defined in table 3 on page 10. the high time is defined as parameter a = (reg0x04 x pixclk_period). figure 6: timing example of pixel data figure 7: row timi ng and frame_valid/ line_valid signals line_valid pixclk d out 9-d out 0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking p a qa qa p . . . . . . . . . number of master clocks frame_valid line_valid
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 10 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor pixel data format preliminary ? . 1adc_mode: reg0xc8, bit 3 = 1: reg0x20, bit 10 reg0xc8, bit 3 = 0: reg0x21, bit 10 (0 = 2 adc mode, 1 = 1 adc mode) default = 0 hblank_reg: reg0xc8, bit 0 = 1: reg0x05 reg0xc8, bit 0 = 0: reg0x07 1adc_mode = 0: minimum value is 202, 1adc_mode = 1: minimum value is 114 default = 396 (13.9 fps) note: for frame rate of 15 fps, set reg0x05 to 272 vblank_reg: reg0xc8, bit 1 = 1: reg0x06 reg0xc8, bit 1 = 0: reg0x08 minimum value: sum of dark and extra rows enabled in reg0x22 and reg0x24 default = 50 pixclk_period: 1adc_mode = 0: reg0x0a, bit 3 - 0 1adc_mode = 1: (reg0x0a, bit 3 - 0) x 2 a value of 0 in the register is not allowed. default = 1 table 3: frame time parameter name equation (master clocks units) default timing at 25 mhz a active data time reg0x04 x pixclk_period (for skip 2x mode: divide reg0x04 by 2, for skip 4x mode: divide reg0x04 by 4) 1,280 pixel clocks = 1,280 master = 51.2s p frame start/end blanking 6 x pixclk_period 6 pixel clocks = 6 master = 0.24s q horizontal blanking hblank_reg x pixclk_period 396 pixel clocks = 396 master = 15.84s a+q rowtime (reg0x04 + hblank_reg) x pixclk_period 1,676 pixel clocks = 1,676 master = 67.04s v vertical blanking vblank_reg x (a + q) + (q - 2 x p) 84,184 pixel clocks = 84,184 master = 3.37ms nrows x (a + q) frame valid time reg0x03 x (a + q) - (q - 2 x p) (for skip 2x mode: divide reg0x03 by 2, for skip 4x mode: divide reg0x03 by 4) 1,715,840 pixel clocks = 1,715,840 master = 68.63ms f total frame time (reg0x03 + vblank_reg) x (a + q) 1,800,024 pixel clocks = 1,800,024 master = 72.0ms
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 11 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor pixel data format preliminary ? the sensor timing is shown in terms of pixe l clock and master clock cycles (please refer to figure 6 on page 9). the recommended mast er clock frequency is 25 mhz. the verti- cal blank and total frame time equations assume that the number of integration rows (reg0x09) is less than or equal to the number of active rows plus blanking rows (reg0x03 + vblank_reg). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 4. table 4: frame time ? long integration time parameter name equation (master clock) default timing v? vertical blanking (long integration time) (reg0x09 ? reg0x03) x (a + q) + (q - 2 x p) 84,184 pixel clocks = 3.37ms f? total frame time (long integration time) (reg0x09) x (a + q) 1,800,024 pixel clocks = 72.0ms
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 12 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor serial bus description preliminary ? serial bus description registers are written to and read from the MT9M011 through the two-wire serial inter- face bus. the sensor is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9m0 1 1 through the serial data (s data ) line. the s data line is pulled up to 2.8v off- chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down? the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as follows: a start bit the slave device 8-bit address a(an) (no) acknowledge bit an 8-bit message a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's 8-bi t address. the last bit of the address deter- mines if the request will be a read or a writ e, where a ?0? indicates a write and a ?1? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the MT9M011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automa tically incremented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the regis- ter data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high.
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 13 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor serial bus description preliminary ? slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? (0xba) in the lsb (lea st significant bit) of the address indicates write mode, and a ?1? (0xb b) indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 14 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor two-wire serial interface sample write and read sequences preliminary ? two-wire serial interface samp le write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 8. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor will give an acknowledge bit. all 16 bits must be written before the regi ster will be updated. after 16 bits are trans- ferred, the register address is automatically in cremented so that the next 16 bits are writ- ten to the next register. the master stop s writing by sending a start or stop bit. figure 8: timing diagra m showing a write to reg0 x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 9. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 9: timing diagra m showing a read from reg0 x09; returned value 0x0284 sclk s data start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk s data start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 15 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor two-wire serial interface sample write and read sequences preliminary ? eight-bit write sequence to be able to write one byte at a time to th e register a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special regist er address (reg0xf1). the register is not updated until all 16 bits have been written. it is not possible to just update half of a regis- ter. in figure 10 a typical sequence for 8-bit wr iting is shown. the second byte is written to the special register (reg0xf1). figure 10: timing diag ram showing a write to re g0x09 with the value 0x0284 eight-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (reg0xf1) the lower 8 bits are accessed (figure 11). the master sets the no-acknowledge bits. figure 11: timing diagra m showing a read from reg0x09; returned value 0x0284 s top re g 0xf1 a c k s tart 0xba addr a c k s data sc lk a c k a c k a c k a c k re g 0x09 0xba addr 0000 0010 1000 0100 s tart s tart 0xbb addr s data sc lk s top na c k a c k a c k a c k re g 0x09 s tart 0xba addr 0000 0010 s tart 0xbb addr s data sc lk na c k a c k a c k a c k re g 0xf1 s tart 0xba addr 1000 0100
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 16 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? registers note: 1 = always 1 0 = always 0 d = programmable ? = read only table 5: register list and default value register number (hex) description data format (binary) default value (hex) 0x00/0xff chip version 0001 0100 0010 0010 (lsb) 0x1433 0x01 row start 0000 0ddd dddd dddd 0x000c 0x02 column start 0000 0ddd dddd dddd 0x001e 0x03 row width 0000 0ddd dddd dddd 0x0400 0x04 column width 0000 0ddd dddd dddd 0x0500 0x05 horizontal blanking b 00dd dddd dddd dddd 0x018c 0x06 vertical blanking b 0ddd dddd dddd dddd 0x0032 0x07 horizontal blanking a 00dd dddd dddd dddd 0x00c6 0x08 vertical blanking a 0ddd dddd dddd dddd 0x0019 0x09 shutter width dddd dddd dddd dddd 0x0432 0x0a row speed ddd0 000d dddd dddd 0x0011 0x0b extra delay 00dd dd dd dddd dddd 0x0000 0x0c shutter delay 00dd dddd dddd dddd 0x0000 0x0d reset d000 00dd 00dd dddd 0x0008 0x1f frame valid control dddd dddd dddd dddd 0x0000 0x20 read mode b dd00 0ddd dddd dddd 0x0200 0x21 read mode a 0000 0d00 0000 dd00 0x040c 0x22 dark col/rows 0000 00dd dddd dddd 0x0129 0x23 flash ??dd dddd dddd dddd 0x0608 0x2b green1 gain 0000 0ddd dddd dddd 0x0020 0x2c blue gain 0000 0d dd dddd dddd 0x0020 0x2d red gain 0000 0ddd dddd dddd 0x0020 0x2e green2 gain 0000 0ddd dddd dddd 0x0020 0x2f global gain 0000 0ddd dddd dddd 0x0020 0xc8 context control d000 0000 d000 dddd 0x000b
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 17 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? table 6: reserved register list and default value register number (hex) description default value (hex) 0x24 reserved 0x806f 0x30 reserved 0x042a 0x31 reserved 0x1c00 0x32 reserved 0x0000 0x33 reserved 0x0349 0x34 reserved 0xc019 0x36 reserved 0xf0f0 0x37 reserved 0x0000 0x3b reserved 0x0021 0x3c reserved 0x1a20 0x3d reserved 0x201e 0x3e reserved 0x2020 0x3f reserved 0x2020 0x40 reserved 0x201c 0x41 reserved 0x00d7 0x42 reserved 0x0777 0x59 reserved 0x000c 0x5a reserved 0xc00f 0x5b reserved ro 0x5c reserved ro 0x5d reserved ro 0x5e reserved ro 0x5f reserved 0x231d 0x60 reserved 0x0080 0x61 reserved 0x0000 0x62 reserved 0x0000 0x63 reserved 0x0000 0x64 reserved 0x0000 0x65 reserved 0x0000 0x70 reserved 0x7b0a 0x71 reserved 0x7b0a 0x72 reserved 0x190e 0x73 reserved 0x180f 0x74 reserved 0x5732 0x75 reserved 0x5634 0x76 reserved 0x7335 0x77 reserved 0x3012 0x78 reserved 0x7902 0x79 reserved 0x7506 0x7a reserved 0x770a 0x7b reserved 0x7809 0x7c reserved 0x7d06 0x7d reserved 0x3110 0x7e reserved 0x007e 0x80 reserved 0x007f
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 18 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? note: writing to these regi sters may cause the part to go into an unknown state. 0x81 reserved 0x007f 0x82 reserved 0x570a 0x83 reserved 0x580b 0x84 reserved 0x470b 0x85 reserved 0x480e 0x86 reserved 0x5b02 0x87 reserved 0x005c 0xf0 reserved 0x0000 0xf5 reserved 0x07ff 0xf6 reserved 0x07ff 0xf7 reserved 0x0000 0xf8 reserved 0x0000 0xf9 reserved 0x007c 0xfa reserved 0x0000 0xfb reserved 0x0000 0xfc reserved 0x0000 0xfd reserved 0x0000 table 6: reserved register list and default value register number (hex) description default value (hex)
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 19 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? table 7: register description bit bit description default (hex) sync?d to frame start bad frame read/ write 0x00/0xff (0/255) chip version 15:0 chip version chip version - read-only. 1433 r 0x01 (1) row start 10:0 row start the first row to be read out (not counting any dark rows that may be read). to window the image down, set this register to the starting y value. setting a value less than 8 is not recommended since the dark rows should be read using reg0x22. 0c y ym w 0x02 (2) column start 10:0 column start the first column to be read out (not counting dark columns that may be read). to window the image down, set this register to the starting x value. setting a value below 24 decimals (0 x18) is not recommended since readout of dark column s should be controlled by reg0x22. 1e y ym w 0x03 (3) row width 10:0 row width number of rows in th e image to be read out (not counting any dark rows or border rows that may be read). 400 y ym w 0x04 (4) column width 10:0 column width number of columns in image to be read out (not counting any dark columns or border columns that may be read). 500 y ym w 0x05 (5) horizontal blanking b 10:0 horizontal blanking b number of blank columns in a row when context b is chosen (reg0xc8, bit 0 = 1) . if set smaller than the minimum value the minimum value will be used. with default settings the minimu m horizontal blanking will be 202 columns when usin g two adcs and 114 columns when using one adc. default of 0x18c = 13.9 fps @ 25 mhz setting of 0x110 = 15 fps @ 25 mhz 18c y ym w 0x06 (6) vertical blanking b 14:0 vertical blanking b number of blank rows in a frame when context b is chosen (reg0xc8, bit 1 = 1). this number must be equal to or larger than the number of dark rows read out in a frame specified by reg0x22. 32 y n w 0x07 (7) horizontal blanking a 10:0 horizontal blanking a number of blank columns in a row when context a is chosen (reg0xc8, bit 0 = 0). the extra columns will be added at the beginning of a row. if set smaller than the minimum value the minimum value will be used. with default settings the minimu m horizontal blanking will be 202 columns when usin g two adcs and 114 columns when using one adc. default of 0xc6 = 27.8 fps @ 25 mhz setting of 0x88 = 30 fps @ 25 mhz c6 y ym w
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 20 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 0x08 (8) vertical blanking a 14:0 vertical blanking a number of blank rows in a frame when context a is chosen (reg0xc8, bit 1 = 1). this number must be equal to or larger than the number of dark rows read out in a frame specified by reg0x22. 19 y n w 0x09 (9) shutter width 15:0 shutter width integration time in numb er of rows. in ad dition to this register the shutter delay register (reg0x0c) and the overhead time will influenc e the integration time for a given row time. 432 y n w 0x0a (10) row speed 3:0 pixel clock period pixel clock period in master clocks when two adcs are used (reg0x20/0x21, bit 10 = 0). the adc clock will always be half the programmed frequency. when only one adc is used the pixel clock frequency will be halved as well, so in this case will be equal to the adc clock frequency. the value ?0? is not allowed, ?1? will be used instead. 1yymw 7:4 delay pixel clock delay pixclk in half master clock cycles. when set the pixel clock can be delayed in increments of half master clock cycles compared to the synchronization of frame_valid, line_valid and data_out. 1n w 8 invert pixel clock invert pixel clock. when set, line_valid, frame _valid, and data_out will be set up to the falling edge of pixclk. when clear, they are set up to the rising edge if there are no delay of the pixel clock. 0n w 15:14 reserved ?0??? 0x0b (11) extra delay 13:0 extra delay extra blanking insert ed between frames specified in pixel clocks. can be used to get a more exact frame rate. it might affect the in tegration times of parts of the image when the integrat ion time is less than one frame. 0y w 0x0c (12) shutter delay 10:0 shutter delay the amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. this variable will automatically be halved when one adc is used so the time in us will remain the same. this register has an upper value de fined by the fact that the reset needs to finish before the readout of that row to prevent changes in the row time. 0ynw table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 21 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 0x0d (13) reset 0 reset setting this bit will pu t the sensor into reset mode, which will set the sensor to its default power-up state. clearing this bit will resume normal operation. 0nymw 1 restart setting this bit will ca use the sensor to abandon the current frame and start resetting the first row. the delay before the first valid fra me is read out equals the integration time. this bit always reads ?0.? 0nymw 2 analog standby 0 = norma l operation (default). 1 = disable analog circuitry. 0nymw 3 chip enable 1 = normal operation. 0 = stop sensor readout. when this is returned to ?1,? sensor readout restarts and starts resetting the starting row in a new frame. to reduce the digital power further the master clock to the sensor can be disabled or the standby pin can be used. 1nymw 4 reserved ?0??? 5 reserved ?0??? 8 show bad frames 1 = output all frames (including bad frames). 0 = only output good frames (default). a bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 0n w 9 restart bad frames when set a restart will be forced to take place when a bad frame is detected. this can shorten the delay when waiting for a good frame, since the delay when masking out a bad frame will be the integration time rather than the full frame time. 0n w 15 synchronize changes 0 = normal operation, update changes to registers that affect image brightness (int egration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any chan ges to these settings until this bit is returned to ?0.? all registers that are frame synchronized will be affected by the setting of this bit. 0n w 0x1f (31) frame_valid control 6:0 early frame_valid rise when enabled, the frame_ valid rising edge will happen for the programmed number of rows before the first line_valid: (bits 6:0) x row time + hori z blank + constant (constant = 3 in default mode). 0n w 7 enable early frame_valid rise 1 = enables the early rise of frame_valid as set in bits 6:0. 0 = default. frame_valid will go high six pixel clocks before first line_valid. 0n w table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 22 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 14:8 early frame_valid fall when enabled the frame_valid falling edge will happen the programmed number of rows before the end of the last line_valid: (1 + bits 14:8) x row time + constant (constant = 3 in default mode). 0n w 15 enable early frame_valid fall 1 = enables the early disabl ing of frame_valid as set in bits 14:8. note that line_valid will still be generated for all active rows. 0 = default. frame_valid will go low six pixel clocks after last line_valid. 0n w 0x20 (32) read mode - context b 0 mirror rows read out rows from bottom to top (upside down). when set, row readout sta rts from row (row start + row size) and continues down to (row start + 1). when clear, readout starts at row start and continues to (row start + row size - 1). this en sures that the starting color is maintained. 0yymw 1 mirror columns read out co lumns from right to left (mirrored). when set, column readout starts fr om column (col start + col size) and continues down to (c ol start + 1). when clear, readout starts at col start and continues to (col start + col size - 1). this ensures that the starting color is maintained. 0yymw 2 row skip 2x - context b when read mode context b is selected (reg0xc8, bit 3 = 1): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13?). 0 = normal readout. 0yymw 3 column skip 2x - context b when read mode context b is selected (reg0xc8, bit 3 = 1): 1 = read out two co lumns, and then skip two columns (as with rows). 0 = normal readout. 0yymw 4 row skip 4x 1 = read ou t two rows, and then skip six rows (i.e. row 8, row 9, row 16, row 17?). 0 = normal readout. 0yymw 5 column skip 4x 1 = read out two colu mns, and then skip six columns (as with rows). 0 = normal readout. 0yymw table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 23 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 7:6 zoom in zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. this is designed to give the contro ller logic time to repeat data to fill in a window that is either 2 or 4 times larger with repeated data. the pixel clock speed is not af fected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. in 2x zoom mode, every row is followed by a blank row (with its own line_valid, but all data bits = 0) of equal time. in 4x zoom mode, every row is followed by three blank rows. the combination of this register and an appropriate change to the window start registers allows the user to zoom to a region of interest withou t affecting the frame rate. 00 = no zoom (default) x1 = zoom 2x 10 = zoom 4x 0yymw 8 over sized when this bit is set a 4-pixel border will be output around the active image a rray independent of readout mode (skip, zoom, mirror, etc.). setting this bit will therefore add eight to th e number of rows and columns in the frame. 0yymw 9 show border this bit in dicates whether to show the border enabled by bit 8. when bit 8 is 0 this bit has no meaning. when bit 8 is 1, this bit decide s whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). 1n w 10 use 1 adc - context b 0 = use both adcs to achieve maximum speed. 1 = use one adc to reduce power. maximum readout frequency is now half of the master clock, and the pixel clock is automatically adju sted as described for the pixel clock speed register. 0yymw 14 continuous line valid 1 = "continuous" line_valid (continue producing line valid during vertical blanking). 0 = normal line_valid (default) no line valid during vertical blanking. 0n w 15 xor line valid 1 = line valid = "c ontinuous" line_valid xor frame valid. 0 = normal line valid. ineffective if continuous line_valid is set. 0n w table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 24 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 0x21 (33) read mode - context a 2 row skip 2x - context a when read mode context a is selected (reg0xc8, bit 3 = 0): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13?). 0 = normal readout. 1yymw 3 column skip 2x - context a when read mode context a is selected (reg0xc8, bit 3 = 0): 1 = read out two co lumns, and then skip two columns (as with rows). 0 = normal readout. 1yymw 10 1 adc mode - context a when read mode context a is selected (reg0xc8, bit 3 = 0): 0 = use both adcs to achieve maximum speed. 1 = use one adc to reduce power. maximum readout frequency is now half of the master clock, and the pixel clock is automatically adju sted as described for the pixel clock speed register. 1yymw 0x22 (34) show control 2:0 number of dark rows specifies the number of dark rows to read out at the beginning of each frame when the dark row readout is enabled (bit 3). the progra mmed number is 1 less than the number of rows. 1nyw 3 enable dark row readout enables the readout of the dark rows specified in bits 2:0. 1nyw 6:4 dark start address the start address for the dark rows. must be set so all dark rows read out falls in the address space 0-7. 2nnw 7 show dark rows when set, the progra mmed dark rows will be output before the active window. frame valid will thus be asserted earlier than normal. this has no effect on integration time or frame rate. whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. all frame synced registers will be updated at this point. 0nnw 8 read dark columns when disabled, an arbitrary number of dark columns can be read out by including them in the active image. enabling the dark columns do not have an effect on the row time, but it will incr ease the minimum horizontal blanking value allowed. 1nyw 9 show dark columns when set, the programmed dark columns will be output before the acti ve pixels in a line. 0nnw 0x23 (35) flash control 7:0 xenon count length of flash_strobe pulse when xenon flash is enabled. the value specifies the length in 1,024 master clock cycle increments. 8nnw 8 led flash enable led flash. when set, the flash_strobe will go on prior to the start of the resetting of a frame. when disabled the flash_strobe will remain high until the finish of the readout of the current frame. 0yyw table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 25 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? 9 every frame 1 = flash should be enabled every frame. 0 = flash should be en abled for 1 frame only. 1nnw 10 end of reset 1 = in xenon mode th e flash should be triggered after the resetting of a frame. 0 = in xenon mode the flash should be enabled after the readout of a frame. 1nnw 12:11 frame delay delay of the flash pulse measured in frames. 0nnw 13 xenon flash enable xenon flash. when set, the output pin flash_strobe will be pulsed high for the programmed period during ve rtical blanking . this is achieved by keeping the inte gration time equal to one frame, and the pulse widt h less than the vertical blanking time. 0ynw 14 reserved ?0??? 15 flash_strobe read-only bit th at indicated whether the flash_strobe pi n is enabled. 0w 0x2b (43) green1 gain 6:0 initial gain init ial gain = bits (6:0) x 0.03125. 20 y n w 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0ynw 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0ynw 0x2c (44) blue gain 6:0 initial gain init ial gain = bits (6:0) x 0.03125. 20 y n w 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0ynw 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0ynw 0x2d (45) red gain 6:0 initial gain init ial gain = bits (6:0) x 0.03125. 20 y n w 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0ynw 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0ynw 0x2e (46) green2 gain 6:0 initial gain init ial gain = bits (6:0) x 0.03125. 20 y n w 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0ynw 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0ynw 0x2f (47) global gain 10:0 global gain this register can be us ed to set all four gains at once. when read, it will return the value stored in reg0x2b. 20 y n w table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 26 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor registers preliminary ? the following notation is used in table 7: sync?d to frame start n = no. the register value will be updated and used immediately. y = yes. the register value will be updated at next frame start as long as the synchronize chan ges bit is 0. note also that frame start is defined as when the first dark row is read out. by default this is eight rows before fr ame_valid goes high bad frame a bad frame is a frame where all rows do not have the same in tegration time, or offsets to the pixel values changed during the frame. n = no. changing the register va lue will not produce a bad frame. y = yes. changing the register va lue might produce a bad frame. ym = yes, but the bad frame will be masked ou t unless the show bad frames feature is enabled. read/write r = read-only register/bit. w = read/write register/bit. 0xc8 (200) context control 0 horizontal blanking select 1 = use horizontal blanki ng context b, reg0x05. 0 = use horizontal blanki ng context a, reg0x07. 1yymw 1 vertical blanking select 1 = use vertical blanking context b, reg0x06. 0 = use vertical blanking context a, reg0x08. 1yymw 2 led flash enable enable led flash. same physic al register as reg0x23, bit 8. 0yyw 3 read mode select 1 = use read mode context b, reg0x20. 0 = use read mode context a, reg0x21. note that bits only found in read mode context b register will always be taken from this register. 1yymw 7 xenon flash enable enable xenon flash. same phys ical register as reg0x23, bit 13. 0ynw 15 restart setting this bit will ca use the sensor to abandon the current frame and start resetting the first row. same physical register as reg0x0d, bit 1. 0nymw table 7: register description (continued) bit bit description default (hex) sync?d to frame start bad frame read/ write
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 27 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? feature description window control reg0x01 row start, reg0x02 column start, r eg0x03 row width, and reg0x04 column width these registers control the size and starting coordinates of the window. by changing these registers, any image format smaller than or equal to sxga can be specified. border of pixels reg0x20, bits 8 and 9 by setting these register bits, a four-pixel border will be added around the specified image. since the border is independent of the readout mode, this border can then be used as extra pixels for image processing algorithms. this means that even in the skip modes, a four-pixel border will be output in the image. when enabled, eight rows and columns must be added to the settings in th e row and column width to get the new win- dow size. if the border is enabled but not sh own in the image (bits 9-8 = 01), eight rows and columns should be added to the horizont al and vertical blanking numbers instead. readout modes column mirror image by setting bit 1 of reg0x20, the readout order of the columns will be reversed as shown in figure 12. the starting color will be preserved when mirroring the columns. row mirror image by setting bit 0 of reg0x20, the readout order of the rows will be reversed as shown in figure 13. the starting color will be preserved when mirroring the rows. figure 12: readout of 6 pixels in no rmal and column mirror output mode figure 13: readout of 6 rows in normal and row mirror output mode g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) r2 (9:0) g2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g3 (9:0) line_valid normal readout d out 9-d out 0 reverse readout d out 9-d out 0 d out 9?d out 0 frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out 9?d out 0 reverse readout row5 (9:0) row6 (9:0) row4 (9:0) row3 (9:0) row2 (9:0) row1 (9:0)
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 28 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? column and row skip by setting bit 3 of reg0x20 (reg0x21), only ha lf of the columns set will be read out, as shown in figure 14. to preserve the bayer pattern in the pixel array pair of columns are read out or skipped. the row skip mode works in the same way, and will read out two rows and then sip two. the row skip works in the same way and will only read out rows with bit 1 equal to ?0.? row skip mode is en abled by setting bit 2 of reg0x20. for both row and column skips, the number of rows or co lumns read out will be half of what is set in reg0x03 or reg0x04, respectively. the sensor can also be programmed to only read out a sixteenth of the specified window size by setting bits 4 and 5 of reg0x20, as sh own in figure 15 (bayer pattern is preserved). figure 14: readout of 8 pixels in no rmal and column skip 2x output mode figure 15: readout of 16 pixels in normal and column skip 4x output mode digital zoom reg0x20, bits 7:6 digital zoom in zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. this is designed to give the controller logic time to repeat data to fill in a window that is either 4 or 16 times larger with repeated data. the pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. in 2x zoom mode, every row is followed by a blank row (with its own line valid, but all data bits = 0) of equal time. in 4x zoom mode, every row is followed by three blank rows. in the zoom modes, reg0x03 and reg0x04 will still specify the window size out of the sensor including the extra blanking, so the active image read out will in effect be a quar ter or a sixteenth of the output image. d out 9?d out 0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) d out 9?d out 0 line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) r2 (9:0) d out 9?d out 0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g7 (9:0) r7 (9:0) d out 9?d out 0 line_valid column skip readout g0 (9:0) r0 (9:0) g4 (9:0) r4 (9:0) ....
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 29 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? figure 16: readout of 8 pixels in normal and zoom 2x output mode frame rate control when a window size is set, the blanking registers (reg0x05-reg0x08) along with the row speed register (reg0x0a) will let you program a desired frame rate. the frame timing equations at the beginning of this document shows you how to calculate the different timings. if these equations are turned around they can help you set the horizontal or ver- tical blanking values to achieve a desired frame rate: hblank_reg = master clock freq / (f rame rate x (reg0x03 + vblank_reg) x pixclk_period) - reg0x04 vblank_reg = master clock freq / (frame rate x (reg0x04 + hblank_reg) x pixclk_period) - reg0x03 readout speeds and power savings the MT9M011 sensor has two adcs to convert the pixel values to digital. since the adcs run at half the master clock frequency, this makes it possible to achieve a data rate equal to the master clock frequency. on the other ha nd, it also makes it an option for slower readout to turn one of the adcs off in order to reduce the power consumption of the sensor. reg0x20 (reg0x21), bit 10, chooses between the two modes: 0 = use both adcs and read out at the se t pixel clock frequency (reg0x0a, bits 3:0) 1 = use 1 adc and read out at half the se t pixel clock frequency (reg0x0a, bits 3:0) this can be used, for example, when the camera is in preview mode. to make the transi- tions between two sensor settings easier, some simple context switching is available in the MT9M011, as described below. context switching reg0xc8 is designed to help switching betw een sensor modes easily. some key registers and bits in the sensor have two physical register locations, called contexts. bits 0, 1, and 3 of reg0xc8 will decide which context of the r egister that is currently in use. a 1 in a bit will choose context b, while a 0 will select co ntext a for that parameter. the select bits can be used in any combination, but by defaul t it is set up to make switching between a preview mode to a full resolution mode easy: full resolution mode: (default) context b: reg0xc8 = 0x000b (context b) reg0x05 = 0x018c (horizontal blanking) reg0x06 = 0x0032 (vertical blanking) reg0x20, bit 10 = 0, bit 3 = 0, bit 2 = 0 (2 adcs, no column or row skip) a full resolution sxga picture will be outp ut at the master clock frequency at 13.9 fps. dout9?dout0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) dout9?dout0 line_valid zoom 2x readout r2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) pixclk pixclk
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 30 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? context a: reg0xc8 = 0x0000 (context a) reg0x07 = 0x00c6 (horizontal blanking) reg0x08 = 0x0019 (vertical blanking) reg0x21, bit 10 = 1, bit 3 = 1, bit 2 = 1 (1 adc, column and row skip enabled) a preview image (half sxga size) will be output at half of the master clock frequency at 27.8 fps. note that the horizontal and vertical blanking values are set so the row time will be pre- served in the two modes. this way, a switch between the modes will not affect the inte- gration time. this is also the reason that the shutter delay register (reg0x0c) is automatically halved in 1 adc mode. a few more control bits are also available through the context register (reg0xc8) so flash and re starting of the sensor can be done at the same time as changing the contexts. see ta ble 7, register description, on page 19 for more information. minimum horizontal blanking the minimum horizontal blanking value is co nstrained by the time used for sampling a row of pixels and the overhead in the readout of a row. this can be expressed in an equa- tion as: min hblank = sampling time + dark col time + overhead 2 adc mode: min hblank = 20 x (reg0x22, bit 8) + 182 = 202 (default) 1 adc mode: min hblank = 20 x (reg0x22, bit 8) + 94 = 114 (default)
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 31 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? valid data signals options line_valid signal by setting bit 9 and 10 of reg0x20, the line _valid signal can be programmed for three different output formats. the formats shown below illustrate reading out four rows and two vertical blanking rows (figure 17). in th e last format, the line_valid signal is the xor between the continuous line_valid signal and the frame_valid signal. figure 17: different line_valid formats frame_valid signal each edge of the frame_valid signal can be programmed to occur earlier than the default time described in the frame timing equa tions. this is useful if a controller chip needs advanced notice that an image is ready and will be read out. reg0x1f is used for this flexibility; table 7, register descriptio n, on page 19 provides more information and equations concerning the time when the frame_valid action will take place. figure 18: fram e_valid signals note: the stippled line_valid pulses are for illu stration purposes only. the rising and falling edges can be programmed independently. default frame_valid line_valid c ontinuously frame_valid line_valid xor frame_valid line_valid line_valid frame_valid re g 0x1f = 0x0000 frame_valid re g 0x1f = 0x8080 frame_valid re g 0x1f = 0x8181
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 32 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? integration time the following registers along with the row time control the integration time: register 0x09: number of rows of integration, default = 0x0432 (1074) register 0x0c: shutter delay, default = 0x0000 (0). this is th e number of pixel clocks that the timing and control logic waits before asserting the reset for a given row the actual total integration time, t int, is: t int = reg0x09 x row time - overhead time - shutter delay where: row time = (reg0x04 + hblank_reg) x pixc lk_period master clock periods overhead time = 64 master clock periods shutter delay = reg0x0c x pixclk_perio d master clock periods in this expression, the row time term, reg0x09 x row time, corresponds to the number of rows integrated. the overhead time (64 master clocks) is the overhead time between the read cycle and the reset cycle, and the final term is the effect of the shutter delay. typically, the value of reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integra- tion time. if reg0x09 is incr eased beyond the total number of rows per frame, MT9M011 will add additional blanki ng rows as needed. a seco nd constraint is that t int must be adjusted to avoid banding in the image from light flicker. under 60hz flicker, this means t int must be a multiple of 1/120 of a second. under 50hz flicker, t int must be a multi- ple of 1/100 of a second. maximum shutter delay the maximum shutter delay is set by the reset cycle time and the overall row time avail- able. it will differ for 1 and 2 adc mode, as shown in the equations below: 2 adc mode: max_shutter_delay = row time - 385 = row time - (365 + 20 x (reg0x22, bit 8)) = row time - (sampling time + resetting time + dark cols + overhead) 1 adc mode: max_shutter_delay = row time - 614 = row time - (574 + 2 x 20 (reg0x22, bit 8)) flash description reg0x23 the MT9M011 supports both xenon and led flash through the flash_strobe output pin. the timing of the flash_strobe pi n with the default settings are shown in figure 19, figure 20, and figure 21. additionally, the flash can be programmed to only be fired once, be delayed by a few frames when asserted, or programmed for other timing, as described in table 7 on page 19. since enabling the led flash will cause one bad frame, where several of the rows only had the flash on for part of their integratio n time, it is recommended to do a restart (reg0x0d, bit 1) of the sensor when enabling the flash. the first bad frame will then be masked out as shown in figure 21.
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 33 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? figure 19: xeno n flash enabled figure 20: led flash enabled (integrat ion time = number of rows in a frame) figure 21: led flash enabled with restart (integration time = number of rows in a frame) frame_valid fla s h_ s trobe ba d frame frame_valid fla s h_ s trobe flash ena b le d ba d frame g oo d frame g oo d frame flash d isa b le d d urin g this frame d urin g this frame flash ena b le d maske d out g oo d frame g oo d frame flash d isa b le d an d a an d a restart frame restart tri gg ere d tri gg ere d frame_valid fla s h_ s trobe maske d out frame
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 34 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor feature description preliminary ? recommended gain settings the gains for green1, blue, red, and green2 pixels are set by registers reg0x2b, reg0x2c, reg0x2d, and reg0x2d, respectively. gain can also be set globally by reg0x2f. the analog gain is set by bits[8:0] of the corresponding register as following: gain = (bit[8] + 1) x (bit[7] + 1) x (bit[6:0]/32) digital gain is set by bits 9 and 10 of the same registers. the analog gain circuitry (pre-adc) is design ed to offer signal gains from 1 to 15.875. the minimum gain of 1 (register set to 0x00 20) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the adc under all specified operating condi- tions. any reduction of the gain below this va lue may cause the sensor to saturate at adc output values less than the maximum, under certain conditions. it is recommended that this guideline be followed at all times. since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise performance to others, while the same overal l gain. table 8 lists the recommended gain settings. table 8: recommended gain settings desired gain recommended settings (gain registers) conversion formula (arithmetic) 1.000 to 1.969 0x020 to 0x03f (register value)/32 2.000 to 7.938 0x0a0 to 0x0ff (register value - 128)/16 8.000 to 15.875 0x1c0 to 0x 1ff (register value - 384)/8
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 35 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? electrical specifications notes: 1. to place the chip in stand by mode, first raise standby to high then wait ten master clock cycles before turning off the master clock. te n master clock cycles are required to place the analog circuitry into standby, low-power mode. 2. summation of currents for all power supplies. table 9: dc electrical characteristics (v dd = v aa = v dd q = 2.8v; t a = 25c; 13.9 fps at 25 mhz) symbol definition conditions min typ max units v ih input high voltage v dd - 0.3 v dd + 0.3 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in = v dd or d gnd -15 15 a v oh output high voltage v dd qv v ol output low voltage 00.2v i oz tri-state output leakage current 15 a i pwr total quiescent supply current 2 clkin = 25 mhz; default settings; c load = 68.5pf 46 68 ma i pwr standby total standby supply current 2 standby = v dd q 1 , clkin = 0 mhz 110a
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 36 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? table 10: ac electrical characteristics t a = ambient = 25c; load capacitance = 68.5pf; master clock frequency = 25 mhz) symbol definition min typ max units f clk _ in input clock frequency clock 125 25 mhz t duty _ cycle input duty cycle 50 % t clk _ jitter input clock jitter % t r input clock rise time ns t f input clock fall time ns t plh p t phl p clkin to pixclk propagation delay low-to-high high-to-low 12 13 ns ns t plh d t phl d clkin to d out <:9:0> propagation delay low-to-high high-to-low 18 15 ns ns t fvsetup setup time for frame_valid be fore rising edge of pixclk 7ns t fvhold hold time for frame_valid after falling edge of pixclk 20 ns t lvsetup setup time for line_valid be fore rising edge of pixclk 8ns t lvhold hold time for line_valid after falling edge of pixclk 25 ns t dsetup setup time for d out before rising edge of pixclk 6ns t dhold hold time for d out after falling edge of pixclk ns t ftol time between rising edge of frame_valid and line_valid 240 ns t outr d out rise time 12 ns t outf d out fall time 11 ns t plhf clkin to frame_valid propag ation delay, low-to-high 7ns t plhl clkin to line_valid propagation delay, low-to-high 7ns t phlf clkin to frame_valid propagation delay, high-to-low 4ns t phll clkin to line_valid prop agation delay, high-to-low 5ns
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 37 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? propagation delay for frame_va lid and line_valid signals the line_valid and frame_valid signals ch ange on the same rising master clock edge as the data output. the line_valid go es high on the same rising master clock edge as the output of the first valid pixel' s data and returns low on the same master clock rising edge as the end of the ou tput of the last valid pixel's data. as shown in the ?output data format? on page 8 and ?output data timing? on page 9, frame_valid goes high 6 pixel clocks prior to the time that the first line_valid goes high. it returns low 6 pixel clocks after the last line_valid goes low. note that the data outputs change on the rising edge of the master clock. figure 22: propagation delays for frame_valid and line_valid signals figure 23: propagation delays fo r pixclk and data out signals figure 24: data output timing diagram c lkin frame_valid line_valid c lkin frame_valid line_valid t plh f, l t phl f, l d out (9:0) d out (9:0) d out (9:0) d out (9:0) d out (9:0) c lkin pix c lk t plh d , t phl d t plh p t r t f t phl p t fv s etup t lv s etup t d s etup t ftol t outr t dhold t lvhold t outf t fvhold pix c lk frame_valid line_valid d out
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 38 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 25: serial host inte rface start co ndition timing figure 26: serial host interface stop condition timing note: all timing are in un its of master clock cycle. figure 27: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 28: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off- chip. sc lk 5 s data 4 sc lk 5 s data 4 sc lk 4 s data 4 sc lk 5 s data
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 39 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? figure 29: acknowledge si gnal timing after an 8- bit write to the sensor figure 30: acknowledge si gnal timing after an 8- bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sc lk s ensor pulls d own s data pin 6 s data 3 sc lk s ensor tri-states s data pin (turns off pull d own) 7 s data 6
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. preliminary: this data sheet contains initial characterization li mits that are subject to change upon full characterization of production devices. MT9M011 - 1/3-inch megapixel image sensor electrical specifications preliminary ? pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 40 ?2004 micron technology, inc. all rights reserved. spectral response figure 31: spectral response 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 350 450 550 650 750 850 950 1050 wavelength (nm) relative response relative spectral response b r g
pdf: 09005aef81051c04/source: 09005aef8102abe8 micron technology, inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - rev. d 1/05 en 41 ?2004 micron technology, inc. all rights reserved. MT9M011 - 1/3-inch megapixel image sensor revision history preliminary ? revision history rev. d, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/05 changed master clock frequency to 25 mhz in table 1, and updated related timings in table 3 added settings for maximum frame ra te and updated description to table 7, register description, on page 19?reg0x05 and reg0x07 changed current values and conditions in tabl e 9, dc electrical characteristics, on page 35 updated table 10, ac electrical characteristics, on page 36 removed icsp package information and ball description rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/04 updated table 5, register list and default value, on page 16 updated table 7, register description, on page 19 rev. b, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/04 updated table 1, key performance parameters, on page 1 updated figure 2 on page 5 replaced ballout drawing updated table 5, register list and default value, on page 16 updated ?electrical specifications? on page 35 rev. a, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . preliminary3/04 original release

▲Up To Search▲

Price & Availability of MT9M011

	To Download MT9M011 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .